Summary:

In this episode, we explore China's struggles to independently produce advanced semiconductor chips, specifically 5nm and 3nm chips and the future to get there and lower. Despite claims of reaching 7nm, China primarily relies on outsourcing for this, and its domestic production is limited to 28nm at scale. The analysis highlights that China faces various obstacles, including a lack of access to crucial equipment like EUV lithography machines, underdeveloped silicon wafer production, limited EDA software availability, and insufficiently advanced cleanroom facilities. While China may theoretically achieve 5nm or 3nm production using workarounds like SAQP, this approach brings significant drawbacks, including high costs, low yields, and energy consumption, making it unlikely to be a viable solution. We discuss all of these things and more in this episode.

Questions to consider as you read/listen:

What are the main technological obstacles preventing China from independently producing 5nm and 3nm chips?

What are the alternative methods China is employing to produce chips at smaller nodes, and what are their limitations?

How does China's current chip production capacity compare to that of other countries, and how are they addressing their weaknesses?

Long format:

China can’t make its own 5nm or 3nm chips under these export restrictions, can it?

The answer is maybe. But it’ll take a lot here is why.

TL;DR:

China is far from making 5nm or 3nm chips at scale domestically due to export restrictions on advanced equipment like EUV lithography. While it can produce limited 7nm chips using inefficient workarounds (like SAQP) and perhaps lower to 5nm or 3nm, yields are low, and costs are extremely high. Core challenges include insufficient silicon wafer production, lack of key EDA design software, and underdeveloped cleanroom facilities. Essentially, without access to advanced tools and technology, China’s chip production is stalled at older nodes (mostly 28nm) and is unlikely to advance soon.

Introduction

The global race for advanced semiconductor technology has placed China at a critical juncture as it contends with strict export restrictions from Western countries. With these limitations, the question arises: can China successfully produce 5nm or even 3nm chips? While some experts and media reports suggest that China is “stuck” at the 7nm node, this narrative oversimplifies the complexities of China’s chip production capabilities. In reality, domestic fabrication is still in its infancy, and challenges across several stages of chip production hinder progress. In this analysis, we delve into China’s technological capabilities, exploring what it has achieved domestically and the significant hurdles it still faces in reaching advanced nodes independently.

CURRENT TALKING POINTS NEED REFINING

Right now, most of the world press and some self-designated subject matter experts say that China is “at 7nm chip [really node size] and is stuck there.”

But that first claim that they are at 7nm is deceptive. China uses other fabricators to get to 7nm. It is not domestic fabrication.

Here’s the real scoop in the charts that follow.

As far as being stuck there, that requires a condition precedent that they are there. The data shows that for AI chips, they aren’t truly at 7nm node size on their own…. well not really as we will see.

In truth and at scale, they are stuck at 28 nm. Shanghai Micro Electronics Equipment (SMEE) claims to have developed a 28 nm lithography machine, the SSA/800-10W. SMEE's current SSA600 series can use 90 nm, 110 nm, and 280 nm processes.

There is an asterisks though. SMIC (a domestic Chinese company) has been able to produce 7 nm chips since 2021, using a technique called "multi-patterning" (more on this latter). But the rejection rate is very very very high and it certainly isn’t at scale. SMIC's 7nm chip production is limited and the yield rate is below 50%, which is well below the industry norm of 90%. SMIC's overall monthly wafer production capacity increased from 714,000 wafers in 2022 to 805,500 wafers in 2023. It is unknown how much of that is 7nm but the best guess in the industry is that due to high rejection rates, it is very low. Otherwise, China would be trumpeting the numbers as they tend to do. SMIC's 7nm chips are very costly, around 10 times the market price of a chip manufactured at TSMC's 7-nm node.

So mostly broken, way undersupplied and way over budget. Not a lot of future there.

For Chinese domestic production of AI chips per the chart above, for GPUs they are at best 28nm, for FPGAs they are at best 40nm, for ASICs they are at best 22nm. To get to 7nm at scale for AI chips they have to outsource and that is predominantly to TSMC. That TMSC door is closed. Taiwan is getting pretty darn aggressive in its written regulations to hurt China.

CAN CHINA GET TO 5nm OR 3nm WITH WHAT IT HAS ON HAND?

Recall getting below 7nm requires ASML EUV or NAEUV lithography systems generally. China has zero EUVs or NAEUVs. They do not even have the high-end older technology DUVs. They have zero of the TWINSCAN NXT:1970i and 1980i DUV immersion lithography systems.

Now back on October 24, 2024, ASML’s CEO Christophe Fouquet stated that China MAY be able to produce 5nm chips or 3nm chips using an older technology DUV equipment. How can this be without EUVs or NAEUVs?

China can potentially make 5nm chips by utilizing workarounds like "self-aligned quadruple patterning (SAQP)" technology on existing Deep Ultraviolet (DUV) lithography machines. Self-aligned quadruple patterning (SAQP) is a lithography technique that increases the density and performance of chips by creating IC patterns from larger pitched patterns on photomasks. SAQP is a spacer-based patterning approach that uses one lithography step and two spacer depositions to reduce lithography resolution by four times. What the heck does that mean? Self-aligned quadruple patterning (SAQP) is a manufacturing technique used to fit more components onto a computer chip, boosting its power and efficiency. Imagine it as a method to create very fine, precise lines needed for chip circuits, starting with a bigger, simpler pattern. In SAQP, only one “printing” step is needed, but the process cleverly adds layers around the initial pattern, almost like building up ridges around a stencil. By adding these layers in just the right way, SAQP divides the original pattern into four, resulting in a much finer design without requiring extra printing steps. This method allows chipmakers to achieve much higher detail than traditional methods, making it possible to produce powerful, compact chips for modern technology. SAQP is also known as a brute-force method because it involves pitch-splitting, which is the division of a pattern into two or three parts. The SAQP process uses repeated plasma deposition and etching steps to pattern fins.

But if the 7nm process using this SAQP process is wasteful with low yields, has high production costs, uses a lot of energy and is not cost competitive compared to using EUV technology, then 5nm or 3nm DUV production using SAQP is going to be perhaps an order of magnitude worse.

But doing the DUV-SAQP route is not easy because it requires technical labor resources (read humans) that China does not currently have.

BUT THERE’S MORE

Recall the lithography is only one part of the ecosystem. Some of the other parts that are worth noting include:

First, there is silicon wafer production. Well-known companies in the production of silicon materials include Shin-Etsu Chemical and SUMCO in Japan, LG Chemical in South Korea, and Global Wafer in Taiwan, China. Although a certain number of companies in mainland China are doing research and development and production of silicon materials, their proportion is still too small. It can be said that the problem of silicon wafer production capacity in the chip manufacturing process is a big mountain on the road of domestic chip development.

Second there is EDA tool software. Electronic Design Automation (EDA) is a specific category of hardware, software, services and processes that use computer-aided design to develop complex electronic systems like printed circuit boards, integrated circuits and microprocessors. The main areas where it can support design work include IC design, electronic circuit design, and PCB design. Currently, the leading EDA software providers globally are Synopsys, Cadence, and Mentor Graphics (now under Siemens), all based in the United States. These three major companies dominate the EDA market, controlling over 90% of the global share. China, however, remains a crucial growth market for these industry giants. Although there are EDA software companies in China, the most prominent one is BGI, which has inherited the early domestic Panda EDA system and has built substantial technological expertise. Despite this, the domestic EDA industry as a whole still faces challenges in achieving a complete process workflow, indicating a significant journey ahead. Without EDA software design, there is no way to design high-end chips.

Third is having the correct environment (clean room). The cleanroom level needed for sub 7nm chips depends on the process, but it's usually ISO 4 (Class 10) or ISO 5 (Class 100). And that is a fascinating discussion for another day.

Conclusion

In summary, China’s path to producing 5nm or 3nm chips domestically is fraught with challenges. While workarounds like self-aligned quadruple patterning (SAQP) theoretically allow for the creation of smaller node sizes, the high costs, low yields, high energy costs, and lack of technical expertise present substantial obstacles. Furthermore, critical components such as silicon wafer production, EDA software, and advanced cleanroom facilities are still underdeveloped in China’s semiconductor ecosystem. Without access to cutting-edge EUV lithography and a robust infrastructure, China’s ambition for advanced chip production remains limited, at least for now.

Sources:

https://itif.org/publications/2024/08/19/how-innovative-is-china-in-semiconductors/#:~:text=Semiconductor%20Manufacturing%20Equipment,-Lithography%20represents%20a&text=Shanghai%20Micro%20Electronics%20Equipment%20(SMEE,the%20SSA/800%2D10W.&text=(By%20comparison%2C%20TSMC%20was%20manufacturing,(See%20figure%208.)

https://swarajyamag.com/tech/how-chinas-state-funded-semiconductor-chipmaker-smic-is-overcoming-us-sanctions-and-developing-a-5-nanometer-chip#:~:text=SMIC%20has%20been%20capable%20of,million%20transistors%20per%20square%20millimeter

https://www.csis.org/analysis/contextualizing-national-security-concerns-over-chinas-domestically-produced-high-end-chip#:~:text=China's%20SMIC%20has%20been%20able,chip%20into%20wide%20commercial%20availability

https://evertiq.com/design/55327

https://www.edn.com/the-truth-about-smics-7-nm-chip-fabrication-ordeal/#:~:text=According%20to%20some%20industry%20observers,design%2C%20which%20implies%20lower%20complexity

https://www.trendforce.com/news/2024/10/24/news-asml-ceo-china-might-be-able-to-produce-5nm-and-3nm-chips-amid-u-s-export-restrictions/#:~:text=Notably%2C%20Fouquet%20claims%20that%20China,to%20the%20report%20from%20Wccftech

https://asiatimes.com/2024/04/china-to-make-5nm-chips-with-saqp-process/

https://www.appliedmaterials.com/eu/en/semiconductor/patterning.html#:~:text=Self%2Daligned%20quadruple%20patterning%20effectively,high%E2%80%91density%20cuts%20and%20vias

https://www.lasertec.co.jp/en/products/glossary/3625.html#:~:text=Self%20Aligned%20Quadruple%20Patterning%20(SAQP,prior%20limitations%20of%20optical%20lithography

https://www.spie.org/news/6378-self-aligned-quadruple-patterning-to-meet-requirements-for-fins-with-high-density#:~:text=Repeated%20plasma%20deposition%20and%20etching,Suong%20Ou%20and%20David%20Hellin

Get full access to GeopoliticsUnplugged Substack at geopoliticsunplugged.substack.com/subscribe

EP66: China can’t make its own 5nm or 3nm chips under these export restrictions, can it? 23:51 Share

Geopolitics Unplugged

Shownotes Transcript

EP66: China can’t make its own 5nm or 3nm chips under these export restrictions, can it?